In a semiconductor memory device such as SDRAM, signals such as a clock signal, an address signal, and a data signal are received by an input buffer circuit first and transmitted to an internal circuit as an internal clock signal, an internal address signal, and an internal data signal respectively. As the speed of semiconductor memory devices increases, a high-speed differential circuit is often used as such an input buffer circuit (refer to Patent Documents 1 and 2).
FIG. 5 is a circuit diagram corresponding to an input buffer circuit described in Patent Document 1. In FIG. 5, the input buffer circuit (input first stage circuit) comprises a differential circuit constituted by N-channel MOS transistors 51 and 52, a differential circuit constituted by P-channel MOS transistors 53 and 54, a differential circuit constituted by N-channel MOS transistors 55 and 56, and a differential circuit constituted by P-channel MOS transistors 57 and 58.
Sources of the N-channel MOS transistors 51 and 52 are connected to each other, and this node N1 is connected to a drain of the N-channel MOS transistor 59. A source of the N-channel MOS transistor 59 is grounded (VSS). Sources of the P-channel MOS transistors 53 and 54 are connected each other, and this connection node N2 is connected to a drain of the P-channel MOS transistor 60. A source of the P-channel MOS transistor 60 is connected to a power supply VDD. Each drain of the N-channel MOS transistors 51 and 52 is connected to each drain of the P-channel MOS transistors 53 and 54.
Sources of the N-channel MOS transistors 55 and 56 are connected to each other, and this connection node N1 is connected to the drain of the N-channel MOS transistor 59. Sources of the P-channel MOS transistors 57 and 58 are connected to each other, and this connection node N2 is connected to the drain of the P-channel MOS transistor 60. Each drain of the N-channel MOS transistors 55 and 56 is connected to each drain of the P-channel MOS transistors 57 and 58.
Gates of the N-channel MOS transistor 51 and the P-channel MOS transistor 53 are connected to each other, and a reference voltage (reference level signal) VREF is applied to them.
Each gate of the N-channel MOS transistor 52 and the P-channel MOS transistor 54 is connected in common to each drain of the N-channel MOS transistors 51 and 52 and the P-channel MOS transistors 53 and 54. Further, gates of the N-channel MOS transistor 56 and the P-channel MOS transistor 58 are connected in common to each drain of the N-channel MOS transistors 51 and 52 and the P-channel MOS transistors 53 and 54.
Gates of the N-channel MOS transistor 55 and the P-channel MOS transistor 57 are connected together, and an external input signal IN such as a command/address signal is applied to them.
An output signal OUT is outputted from a node between the drains of the N-channel MOS transistors 55 and 56 and the drains of the P-channel MOS transistors 57 and 58 via an inverter circuit 11.
Since the input buffer circuit is constituted as a differential circuit as described, a direct current (short-circuit current, i.e., a power supply current) flows even during standby mode. Therefore, using a power control signal PWDN and an inverted signal PWDN_B of the power control signal PWDN, the input buffer circuit is activated when the external input signal IN is received, and the power supply to the input buffer circuit is cut off during the standby mode.
The power control signal PWDN is supplied to a gate of the N-channel MOS transistor 59 and the inverted signal PWDN_B of the power control signal PWDN is supplied to a gate of the P-channel MOS transistor 60. When the power control signal PWDN is at a high level, the N-channel MOS transistor 59 and the P-channel MOS transistor 60 become conductive, and the input buffer circuit is activated. On the other hand, when the power control signal PWDN is at a low level, the N-channel MOS transistor 59 and the P-channel MOS transistor 60 become nonconductive, the power supply to the input buffer circuit is cut off.
Further, Patent Document 3 discloses an input buffer circuit having a differential amplifier circuit that receives an external input signal and a reference voltage for determining the level of the input signal, a transistor for a first operating current path that supplies a predetermined first operating current to the differential amplifier circuit and that always remains ON due to a predetermined fixed voltage supplied to its gate, and at least one transistor for a second operating current path that supplies a second operating current greater than the first operating current to the differential amplifier when in the ON state and that is ON/OFF controlled according to an external control signal.    [Patent Document 1] Japanese Patent Kokai Publication No. JP-P2009-104694A    [Patent Document 2] Japanese Patent Kokai Publication No. JP-A-11-266152    [Patent Document 3] Japanese Patent Kokai Publication No. JP-P2003-258624A